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NIELIT CoE Noida Recruitment 2026 | Walk-in for VLSI Engineer

NIELIT CoE Noida Recruitment 2026 – Walk-in Interview for VLSI Design Expert & Junior VLSI Engineer

The National Institute of Electronics and Information Technology (NIELIT), Centre of Excellence in Chip Design, Noida has released a detailed advertisement for recruitment of VLSI Design Expert / Junior VLSI Engineer on a purely contractual basis for one year.

Eligible candidates can appear for Document Verification and Walk-in Interview on 25 February 2026 at NIELIT CoE Noida.


πŸ”” Short Information – NIELIT CoE Noida Recruitment 2026

Particulars

Details

Organization

NIELIT – Centre of Excellence in Chip Design

Location

Noida (Sector-29)

Advertisement No.

NIELIT/NOIDA/CoE/2026/04

Post Name

VLSI Design Expert / Junior VLSI Engineer

Total Vacancies

02

Tenure

1 Year (Contract)

Salary

β‚Ή40,000 per month (CTC)

Walk-in Date

25 February 2026

Registration Fee

β‚Ή500 (Non-refundable)


πŸ“… Important Dates – NIELIT CoE Noida Recruitment 2026

Event

Date

Walk-in Interview

25-02-2026

Document Verification

09:30 AM – 11:30 AM

Interview Time

11:00 AM onwards

Reporting Deadline

Before 02:00 PM


πŸ“Œ Vacancy Details – NIELIT CoE Noida Recruitment 2026

Post

No. of Posts

Salary

Age Limit

VLSI Design Expert / Junior VLSI Engineer

02

β‚Ή40,000 PM (CTC)

Up to 45 Years


πŸŽ“ Eligibility Criteria – NIELIT CoE Noida Recruitment 2026

Essential Qualification

βœ” Master’s Degree in:

  • Electronics & Communication Engineering
  • Electrical Engineering
  • VLSI Design
  • Related Field

OR

βœ” Bachelor’s Degree in above fields with 2 years experience


πŸ’Ό Job Responsibilities – NIELIT CoE Noida Recruitment 2026

  • Design & development of reusable IP blocks using open-source EDA tools
  • Develop academic & practical content in domains like:
    • RTL Design & Integration
    • Physical Design
    • Synthesis & STA
    • DFT & ATPG
    • Analog & Mixed Signal Design
  • Create design labs using tools such as:
    • Magic, KLayout, Yosys, OpenROAD, Ngspice, Verilator, etc.
  • Mentor junior engineers and interns
  • Develop reproducible VLSI design projects

⭐ Preferred Skills – NIELIT CoE Noida Recruitment 2026

  • Teaching or curriculum development experience
  • Knowledge of FPGA learning kits
  • Familiarity with LMS platforms (Moodle)
  • Strong communication skills

πŸ“ Application Process – NIELIT CoE Noida Recruitment 2026

1.     Pay β‚Ή500 registration fee online (PNB Account – NIELIT Gorakhpur Centre).

2.     Fill application form and attach:

o    Self-attested documents

o    Payment receipt

3.     Bring original documents for verification.

4.     Appear for Document Verification & Walk-in Interview.

πŸ“ Venue:
NIELIT CoE Noida
PS-1D, Behind Brahmaputra Shopping Complex
Sector-29, Noida – 201303


⚠ Important Instructions – NIELIT CoE Noida Recruitment 2026

  • No application via post will be accepted
  • Only candidates clearing document verification can attend interview
  • No TA/DA will be paid
  • Engagement is purely contractual
  • Empanelment does not guarantee deployment

 


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❓ FAQs – NIELIT CoE Noida Recruitment 2026

Q1. How many vacancies are available?
πŸ‘‰ 02 posts.

Q2. What is the salary?
πŸ‘‰ β‚Ή40,000 per month (CTC).

Q3. What is the interview date?
πŸ‘‰ 25 February 2026.

Q4. Is there any application fee?
πŸ‘‰ Yes, β‚Ή500 (non-refundable).

Q5. Is this a permanent government job?
πŸ‘‰ No, it is contractual for one year.

 


 

 

Disclaimer

The exam results and marks published on this website are meant solely for the convenience of candidates and should not be considered as official or legally binding documents. While we have made every effort to ensure the accuracy of the information provided, we cannot accept responsibility for any unintentional mistakes that may appear in the results or marks. Additionally, we disclaim any liability for any loss or damage that may arise due to inaccuracies, omissions, or errors in the information displayed on this site.

 

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